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-- Company: 
-- Engineer: 
-- 
-- Create Date:	   16:54:32 04/07/2009 
-- Design Name: 
-- Module Name:	   MBR_register - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MBR_register is
  generic(
    N : integer := 32
    );
  port (MemData_IN   : in  std_logic_vector (7 downto 0);
	 Uint_OE_IN  : in  std_logic;
	 Sint_OE_IN  : in  std_logic;
	 mem_RE	     : in  std_logic;
	 CLK_IN	     : in  std_logic;
	 BusData_OUT : out std_logic_vector (N-1 downto 0);
	 MBR_OUT     : out std_logic_vector (7 downto 0));
end MBR_register;

architecture Behavioral of MBR_register is
  signal content       : std_logic_vector(7 downto 0) :=  (others => '0');
  signal output_select : std_logic_vector(1 downto 0);
begin
  output_select <= Uint_OE_IN & Sint_OE_IN;
  with output_select select
    BusData_OUT <= ext(content, N) when "10",
    sxt(content, N)		   when "01",
    (others => 'Z')		   when others;  
        
  MBR_OUT <= content;

  process(CLK_IN)
  begin
    if(CLK_IN = '1' and CLK_IN'event) then
      -- Latch Input
      content <= content;
      if(mem_RE = '1') then
	content <= MemData_IN;
      end if;
    end if;
  end process;
end Behavioral;

